Low stress conductive polymer bump
US7170187B2 · kind B2 · utility
5Cited by
21References
5Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 31, 2004 |
| Grant date | Jan 30, 2007 |
| Priority date | — |
| Expiry date | Aug 31, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/1025
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Disclosed is a laminated (or non-laminated) conductive interconnection for joining an integrated circuit device to a device carrier, where the conductive interconnection comprises alternating metal layers and polymer layers. In addition, the polymer can include dendrites, metal projections from the carrier or device, and/or micelle brushes on the outer portion of the polymer. The polymer layers include metal particles and the alternating metal layers and polymer layers form either a cube-shaped structure or a cylinder-shaped structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.