Test mode for detecting a floating word line
US7170804B2 · kind B2 · utility
3Cited by
2References
22Claims
0Family size
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Key dates
| Filing date | Apr 5, 2005 |
| Grant date | Jan 30, 2007 |
| Priority date | — |
| Expiry date | Jul 20, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/1202
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Devices and methods that allow floating word lines in memory arrays to be detected are provided. By driving local word lines from each side with divided drive lines, local word lines on one side of the memory array may be set to an predetermined voltage level (e.g., an intermediate voltage level between VPP and VNWLL). After disconnecting the local word lines on the one side, memory cells on the other side may be tested for read failures, which may indicate floating word lines on the one side.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.