Self-testing circuit in semiconductor memory device
US7171592B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 10, 2003 |
| Grant date | Jan 30, 2007 |
| Priority date | — |
| Expiry date | Jul 30, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/848
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes a self-testing circuit and a self-redundancy circuit with simple structures. The self-testing circuit includes a comparison circuit which compares write data with read data with respect to normal memory blocks and redundant memory blocks, and a decision circuit which decides if the semiconductor memory device is good or defective based on the plurality of comparison result signals. A signal transfer and holding circuit is connected between the comparison circuit and the decision circuit to transfer the plurality of comparison result signals to the decision circuit and to supply the plurality of comparison result signals to the self-redundancy circuit as a test result.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.