Method of forming multiple gate insulators on a strained semiconductor heterostructure
US7172935B2 · kind B2 · utility
5Cited by
18References
11Claims
0Family size
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Key dates
| Filing date | Dec 17, 2004 |
| Grant date | Feb 6, 2007 |
| Priority date | — |
| Expiry date | Dec 17, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/514
Abstract
A method for forming multiple gate insulators on a strained semiconductor heterostructure, including the steps of oxidation and deposition.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.