Method of fabricating an embedded non-volatile memory device
US7172940B1 · kind B1 · utility
33Cited by
6References
7Claims
0Family size
Assignee
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Key dates
| Filing date | Sep 15, 2005 |
| Grant date | Feb 6, 2007 |
| Priority date | — |
| Expiry date | Sep 15, 2025 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/954
Abstract
A method of fabricating a non-volatile memory based on SONOS is disclosed. By masking the peripheral circuit area with a reverse ONO photoresist layer, the residual ONO layer that is not covered by a gate within the memory array area is etched away to expose the substrate. After the etching of the ONO layer, a channel adjustment doping is carried out subsequently using the reverse ONO photoresist layer as an implant mask, thereby forming lightly doped regions next to the gate within the memory array area. Finally, the reverse ONO photoresist layer is then stripped.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.