Process for fabricating an integrated electronic circuit that incorporates air gaps
US7172980B2 · kind B2 · utility
32Cited by
5References
12Claims
0Family size
Assignees
Inventors
Key dates
| Filing date | Feb 18, 2004 |
| Grant date | Feb 6, 2007 |
| Priority date | — |
| Expiry date | Jul 23, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A process for fabricating an integrated electronic circuit comprises the formation of at least one air gap between interconnect elements above only a defined portion of a surface of a substrate, within an interconnect layer. The interconnect layer comprises a sacrificial material and extends beneath an intermediate layer of permeable material. The air gap is formed by removal, through the intermediate layer, of at least part of the sacrificial material by bringing the permeable material into contact with an agent for removing the sacrificial material, to which agent the permeable material is resistant.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.