Integrated circuit arrangement having capacitors and having planar transistors and fabrication method

US7173302B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Ralf Brederlow · Poing, DE
• Jessica Hartwich · Neubiberg, DE
• Christian Pacha · Birkenfeld, DE
• Wolfgang Rosner · Hersbruck, DE
• Thomas Schulz · Austin, US

Key dates

• Filing date: Oct 10, 2003
• Grant date: Feb 6, 2007
• Expiry date: Oct 10, 2023

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D86/201

Abstract

An integrated circuit arrangement and method of fabricating the integrated circuit arrangement is described. The integrated circuit arrangement contains an insulating region and a sequence of regions which forms a capacitor. The sequence contains a near electrode region near the insulating region, a dielectric region, and a remote electrode region remote from the insulating region. The insulating region is part of an insulating layer arranged in a plane. The capacitor and an active component are arranged on the same side of the insulating layer and form a memory cell. The near electrode region and an active region of the component are arranged in a plane which lies parallel to the plane in which the insulating layer is arranged. A processor is also contained in the integrated circuit arrangement.