3.5 transistor non-volatile memory cell using gate breakdown phenomena
US7173851B1 · kind B1 · utility
43Cited by
2References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 18, 2005 |
| Grant date | Feb 6, 2007 |
| Priority date | — |
| Expiry date | Oct 18, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C17/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A programmable memory cell formed useful in a memory array having column bitlines and row wordlines. The memory cell including a breakdown transistor having its gate connected to a program wordline and a write transistor connected in series at a sense node to said breakdown transistor. The gate of the write transistor is connected to a write wordline. Further, a first sense transistor has its gate connected to the sense node. A second sense transistor is connected in series to the first sense transistor and has its gate connected to a read wordline. The second sense transistor has its source connected to a column bitline.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.