Method for sampling phase control
US7173993B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 16, 2002 |
| Grant date | Feb 6, 2007 |
| Priority date | — |
| Expiry date | Jul 21, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0337
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Method for sampling phase control for clock and data recovery of a data signal includes sampling a received data signal with a first sampling signal comprising equidistant sampling pulses, minimizing phase deviation between the first sampling signal and the phase of the received data signal to generate an adjusted second sampling signal, and sampling the received data signal with the adjusted second sampling signal to generate sampling data values. The method also includes integrating the sampling data values of the sampled data signal to form a summation value, and altering the phase of sampling pulses of the adjusted second sampling signal until the integrated summation value exceeds a threshold value that can be set.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.