Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions
US7176483B2 · kind B2 · utility
54Cited by
28References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 7, 2004 |
| Grant date | Feb 13, 2007 |
| Priority date | — |
| Expiry date | Jan 7, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/62
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An electrical junction that includes a semiconductor (e.g., C, Ge, or an Si-based semiconductor), a conductor, and an interface layer disposed therebetween. The interface layer is sufficiently thick to depin a Fermi level of the semiconductor, yet sufficiently thin to provide the junction with a specific contact resistance of less than or equal to approximately 1000 Ω-μm2, and in some cases a minimum specific contact resistance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.