Inventor · Palo Alto, CA, US

Daniel E. Grupp

47Patents
15h-index
19Co-inventors
78Inventor score

Filing activity: Nov 3, 1994 → Apr 8, 2024

Most-cited inventions

PatentTitleAreaCited byStatus
US6891234B1 Transistor with workfunction-induced charge layer Electricity 157 Expired
US6236033A Enhanced optical transmission apparatus utilizing metal films having apertures and periodic surface topography Performing Operations; Transporting 100 Expired
US7112478B2 Insulated gate field effect transistor having passivated Schottky barriers to the channel Emerging Cross-Sectional Technologies 77 Expired
US6198113A Electrostatically operated tunneling transistor Emerging Cross-Sectional Technologies 56 Expired
US7176483B2 Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions Electricity 54 Expired
US7084423B2 Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions Electricity 49 Expired
US9232959B2 Multi fluid tissue resection methods and devices Human Necessities 38 Active
US7382021B2 Insulated gate field-effect transistor having III-VI source/drain layer(s) Electricity 25 Expired
US6833556B2 Insulated gate field effect transistor having passivated schottky barriers to the channel Emerging Cross-Sectional Technologies 23 Expired
US7884003B2 Method for depinning the fermi level of a semiconductor at an electrical junction and devices incorporating such junctions Electricity 23 Active
US7462860B2 Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions Electricity 21 Expired
US9209261B2 Method for depinning the fermi level of a semiconductor at an electrical junction and devices incorporating such junctions Electricity 20 Active
US7883980B2 Insulated gate field effect transistor having passivated schottky barriers to the channel Emerging Cross-Sectional Technologies 18 Active
US8263467B2 Process for fabricating a self-aligned deposited source/drain insulated gate field-effect transistor Electricity 16 Active
US9425277B2 Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions Electricity 16 Active
US9461167B2 Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions Electricity 15 Active
US8658523B2 Method for making semiconductor insulated-gate field-effect transistor having multilayer deposited metal source(s) and/or drain(s) Electricity 15 Active
US10090395B2 Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions Electricity 15 Active
US9905691B2 Method for depinning the fermi level of a semiconductor at an electrical junction and devices incorporating such junctions Electricity 15 Active
US7816240B2 Method for making semiconductor insulated-gate field-effect transistor having multilayer deposited metal source(s) and/or drain(s) Electricity 13 Active
US8916437B2 Insulated gate field effect transistor having passivated schottky barriers to the channel Emerging Cross-Sectional Technologies 12 Active
US8377767B2 Insulated gate field effect transistor having passivated schottky barriers to the channel Emerging Cross-Sectional Technologies 11 Active
US8766336B2 Method for depinning the fermi level of a semiconductor at an electrical junction and devices incorporating such junctions Electricity 10 Active
US5586064A Active magnetic field compensation system using a single filter Physics 10 Expired
US8431469B2 Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions Electricity 10 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.