Circuit and method for operating a delay-lock loop in a power saving manner
US7177208B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 11, 2005 |
| Grant date | Feb 13, 2007 |
| Priority date | — |
| Expiry date | Mar 11, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2227
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A control circuit for a delay-lock loop having a delay line and a phase detector is used in a memory device. In a standby mode, the control circuit isolates a reference clock signal from the delay-lock loop to save power unless a clock signal generated by the loop is needed for a memory operation. However, the reference signal is periodically coupled to the delay line for a sufficient period to achieve a locked condition. As a result, the phase of the output signal from delay-lock loop can be quickly locked to the phase of the reference signal when a memory operation is to occur during a normal operating mode. When transitioning between the standby mode and the normal operating mode, the control circuit couples the reference clock signal to the delay line for at least a predetermined period of time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.