Manufacturing method and apparatus to avoid prototype-hold in ASIC/SOC manufacturing
US7178115B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 11, 2003 |
| Grant date | Feb 13, 2007 |
| Priority date | — |
| Expiry date | Apr 29, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/90
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A manufacturing process for LSIs uses an event tester simulator and an event tester to avoid prototype hold. In the LSI manufacturing method an LSI is designed under an EDA (electronic design automation) environment to produce design data of a designed LSI, and logic simulation is performed on a device model of the LSI design in the EDA environment with use of a testbench and producing a test vector file of an event format as a result of the logic simulation. Then, simulation data files are verified with use of the design data and the testbench by operating an event tester simulator, and a prototype LSI is produced through a fabrication provider by using the design data. The prototype LSI is tested by an event tester by using the test vector file and the simulation data files and test results is feedbacked to the EDA environment or the fabrication provider.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.