Lead frame for improving molding reliability and semiconductor package with the lead frame
US7180161B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 19, 2005 |
| Grant date | Feb 20, 2007 |
| Priority date | — |
| Expiry date | Jan 19, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/351
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A lead frame for improving molding reliability and a semiconductor package with the lead frame are proposed. At least one embossed structure, such as a metal bump or recessed portion, is formed on a bonding layer of a wire-bonding area of the lead frame. At least one semiconductor chip is electrically connected to the lead frame via bonding wires bonded to the bonding layer. During a molding process for fabricating an encapsulant to encapsulate the chip, the bonding wires and a portion of the lead frame, the embossed structure makes the bonding layer become uneven and thus increases the contact area and adhesion between the bonding layer and the encapsulant, so as to prevent cracks of the bonding wires and improve the electrical performances and molding reliability.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.