Patent · US Expired

Integrated semiconductor memory comprising at least one word line and comprising a multiplicity of memory cells

US7180820B2 · kind B2 · utility

2Cited by

3References

23Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Jorg Kliewer · Birkenfeld, DE
Herbert Benzinger · Birkenfeld, DE
Manfred Proll · Dorfen, DE
Stephan Schröder · Birkenfeld, DE

Key dates

Filing date	May 27, 2005
Grant date	Feb 20, 2007
Priority date	—
Expiry date	May 27, 2025

Classification

Technology area (CPC H)Electricity
CPC primaryH10B12/488
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

An integrated semiconductor memory includes at least one word line and a number of memory cells. Each memory cell has a selection transistor coupled to the word line. A word line driver is coupled to the word line. The word line driver provides a first electrical potential or a second electrical potential to the word line such that the word line is activated by the first electrical potential and is deactivated by the second electrical potential. A passive component (e.g., a diode or a resistor) is coupled between the word line and the second electrical potential such that the word line is coupled to the second electrical potential in a high-resistance fashion through the passive component. The passive component is transmissive for a leakage current between the word line and the contact connection.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.