Patent · US Expired

Integrated memory having redundant units of memory cells and method for testing an integrated memory

US7181579B2 · kind B2 · utility

1Cited by

5References

7Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Aurel von Campenhausen · Munich, DE
Manfred Proll · Dorfen, DE
Jorg Kliewer · Birkenfeld, DE
Stephan Schröder · Birkenfeld, DE

Key dates

Filing date	Mar 12, 2004
Grant date	Feb 20, 2007
Priority date	—
Expiry date	Feb 11, 2025

Classification

Technology area (CPC G)Physics
CPC primaryG11C2029/4402
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

An integrated memory has individually addressable normal and redundant units of memory cells. A memory unit is used to store, in a normal mode, an address for one of the normal units which needs to be replaced by one of the redundant units. A comparison unit compares an address which is present on an address bus with an address stored in the memory unit and activates one of the redundant units in the event of a match being identified. The memory also has a test circuit which can be activated by a test mode signal, can reset the memory unit to an initial state, and can store an address for one of the redundant units in the memory unit for subsequently writing an identification code to this redundant unit.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.