Method of manufacturing field effect transistor
US7183149B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 14, 2005 |
| Grant date | Feb 27, 2007 |
| Priority date | — |
| Expiry date | Sep 14, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/015
Abstract
Provided is a method of manufacturing a field effect transistor (FET). The method includes steps of: forming an ohmic metal layer on a substrate in source and drain regions; sequentially forming an insulating layer and a multilayered resist layer on the entire surface of the resultant structure and simultaneously forming resist patterns having respectively different shapes in both a first region excluding the ohmic metal layer and a second region excluding the ohmic metal layer, wherein a lowermost resist pattern is exposed in the first region, and the insulating layer is exposed in the second region; exposing the substrate and the insulating layer by simultaneously etching the exposed insulating layer and the exposed lowermost resist pattern using the resist patterns as etch masks, respectively; performing a recess process on the exposed substrate and etching the exposed insulating layer to expose the substrate; and forming gate recess regions having different etching depths from each other over the substrate, depositing a predetermined gate metal, and removing the resist patterns. In this method, transistors having different threshold voltages can be manufactured without addition…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.