Method of manufacturing self aligned non-volatile memory cells
US7183153B2 · kind B2 · utility
14Cited by
82References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 12, 2004 |
| Grant date | Feb 27, 2007 |
| Priority date | — |
| Expiry date | Apr 12, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/035
Abstract
A method of forming an array of non-volatile memory cells includes forming a plurality of floating gate structures and shaping the plurality of floating gate structures to reduce the width of upper parts of floating gate structures. A first process forms floating gates by etching an upper portion of a polysilicon structure with masking elements in place to shape the floating gate. A second process etches recesses and protrusions in a polysilicon structure prior to etching the structure to form individual floating gates.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.