Silicon-on-insulator wafer transfer method using surface activation plasma immersion ion implantation for wafer-to-wafer adhesion enhancement
US7183177B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 16, 2004 |
| Grant date | Feb 27, 2007 |
| Priority date | — |
| Expiry date | Apr 28, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A method of fabricating a semiconductor-on-insulator structure from a pair of semiconductor wafers, includes forming an oxide layer on at least a first surface of a first one of the wafers and performing a bonding enhancement implantation step by ion implantation of a first species in the first surface of at least either of the pair of wafers. The method further includes performing a cleavage ion implantation step on one of the pair of wafers by ion implanting a second species to define a cleavage plane across a diameter of the wafer at the predetermined depth below the top surface of the one wafer. The wafers are then bonded together by placing the first surfaces of the pair of wafers onto one another so as to form an semiconductor-on-insulator structure. The method also includes separating the one wafer along the cleavage plane so as to remove a portion of the one wafer between the second surface and the cleavage plane, whereby to form an exposed cleaved surface of a remaining portion of the one wafer on the semiconductor-on-insulator structure. Finally, the cleaved surface is smoothed, preferably by carrying out a low energy high momentum ion implantation step.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.