IC with comparator receiving expected and mask data from pads
US7183570B2 · kind B2 · utility
4Cited by
2References
5Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 11, 2005 |
| Grant date | Feb 27, 2007 |
| Priority date | — |
| Expiry date | Apr 11, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31926
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Test circuits located on semiconductor die enable a tester to test a plurality of die/ICs in parallel by inputting both stimulus and response patterns to the plurality of die/ICs. The response patterns from the tester are input to the test circuits along with the output response of the die/IC to be compared. The response patterns include one of expected data and mask data input on an output pad of the die/IC and the other of expected data and mask data input on another pad of the die/IC, which may be an input pad or an output pad. In addition to functional testing, scan testing of die and ICs is also possible.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.