Metal line having an increased resistance to electromigration along an interface of a dielectric barrier layer by implanting material into the metal line
US7183629B2 · kind B2 · utility
4Cited by
1References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 30, 2004 |
| Grant date | Feb 27, 2007 |
| Priority date | — |
| Expiry date | Jan 25, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
During the formation of a metallization layer of a semiconductor device, a cap layer is formed above a metal line and subsequently an implantation process is performed so as to modify the metal in the vicinity of the interface between the cap layer and the metal line. Consequently, an improved behavior in view of electromigration of the metal line may be obtained, thereby increasing device reliability.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.