Logic process DRAM
US7184290B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 27, 2005 |
| Grant date | Feb 27, 2007 |
| Priority date | — |
| Expiry date | May 27, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/482
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A dynamic random access memory (DRAM) unit includes pluralities of bit line pairs and word lines. Each bit line pair includes first and second bit lines aligned with each other in an end-to-end arrangement. The first bit lines are arranged substantially parallel and consecutively adjacent to one another. The second bit lines are arranged substantially parallel and consecutively adjacent to one another. Each word line is associated with either the first bit lines or the second bit lines. A first array is formed by the first bit lines and the associated word lines. A second array is formed by the second bit lines and the associated word lines. Each of a plurality of memory cells is associated with every other bit line along each word line. Each of a plurality of multiplexers is in communication with two adjacent bits lines within one of the first and second arrays.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.