Electronic memory apparatus, and method for deactivating redundant bit lines or word lines
US7184335B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 8, 2005 |
| Grant date | Feb 27, 2007 |
| Priority date | — |
| Expiry date | Aug 24, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/83
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Electronic memory apparatus, and method for deactivating redundant bit lines or word linesAn electronic memory apparatus (100) having a memory cell array (101), a column address decoding unit (102) for decoding a column addressing signal (105) and for actuating an addressed bit line in the memory cell array (101), a column redundancy activation unit (103) for activating a redundant bit line when a currently used bit line has been determined to be faulty during testing of the memory apparatus (100), a row address decoding unit (202) for decoding a row addressing signal (205) and for actuating an addressed word line in the memory cell array (101), and a row redundancy activation unit (203) for activating a redundant word line when a currently used word line has been determined to be faulty during testing of the memory apparatus (100). A column deactivation unit deactivates unused, redundant bit lines and those bit lines which have been determined to be faulty during testing of the memory apparatus, and a row deactivation unit (204) deactivates unused, redundant word lines and those word lines which have been determined to be faulty during testing of the memory apparatus (100).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.