High-speed interface circuit for semiconductor memory chips and memory system including semiconductor memory chips

US7184360B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Peter Gregorius · Munich, DE
• Martin Streibl · Petershausen, DE
• Paul Wallner · Prien am Chiemsee, DE
• Thomas Rickes · Munich, DE

Key dates

• Filing date: Jun 15, 2005
• Grant date: Feb 27, 2007
• Expiry date: Sep 15, 2025

Classification

• Technology area (CPC G): Physics
• CPC primary: G11C2207/107
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A high-speed interface circuit is implemented in a semiconductor memory chip including a memory core, a first interface circuit section, and a second interface circuit section. The first interface circuit section is connectable to a write data-/command and address signal bus, includes a write data-/command and address re-driver/transmitter path (which may be transparent) and does not include any clock signal synchronizing circuitry, and a main write signal path including a serial-to-parallel converting and synchronizing device to synchronize with a reference clock signal received write data-/command and address signals and delivering the parallel converted write signals to the memory core. The second interface circuit section is connectable to a read data bus and includes a transparent read data re-driver/transmitter path for transmitting and re-driving received serial read data to a succeeding semiconductor memory chip and a main read signal path for inserting the parallel-to-serial converted read data from the memory core into the received serial read data stream, synchronizing the parallel-to-serial converted read data with the reference clock signal and providing the serialized…