Method and apparatus for application-specific programmable memory architecture and interconnection network on a chip
US7185309B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 30, 2004 |
| Grant date | Feb 27, 2007 |
| Priority date | — |
| Expiry date | Mar 6, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/331
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Programmable architecture for implementing a message processing system using an integrated circuit is described. In an example, specification data is received that includes attributes of the memory system. A logical description of the memory system is generated in response to the specification data. The logical description defines a memory component and a memory-interconnection component. A physical description of the memory system is generated in response to the logical description. The physical description includes memory circuitry associated with the integrated circuit defined by the memory component. The memory circuitry includes an interconnection topology defined by the memory interconnection component.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.