Vertical diode formation in SOI application
US7186596B2 · kind B2 · utility
8Cited by
2References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 21, 2005 |
| Grant date | Mar 6, 2007 |
| Priority date | — |
| Expiry date | Jun 21, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/611
Abstract
A method for making a semiconductor device is provided. The method comprises (a) providing a semiconductor stack comprising a semiconductor substrate (203), a first semiconductor layer (205), and a first dielectric layer (207) disposed between the substrate and the first semiconductor layer; (b) forming a first trench in the first dielectric layer which exposes a portion of the substrate; (c) forming a first doped region (209) in the exposed portion of the substrate; and (d) forming anode (211) and cathode (213) regions in the first implant region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.