Power transistor arrangement and method for fabricating it

US7186618B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Martin Pölzl · Ossiach, AT
• Franz Hirler · Isen, DE
• Oliver Häberlen · Villach, AT
• Manfred Kotek · Villach, AT
• Walter Rieger · Arnoldstein, AT

Key dates

• Filing date: Oct 29, 2004
• Grant date: Mar 6, 2007
• Expiry date: Apr 16, 2025

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/519

Abstract

When fabricating trench power transistor arrangements (1) with active cell array trenches (5) and passive connecting trenches (6), the cell array trenches (5) are provided in greater width than the connecting trenches (6). An auxiliary layer (24) is deposited conformally onto a lower field electrode structure (11) in the cell array trenches (5) and the connecting trenches (6) and is etched back as far as the top edge in the connecting trenches (6), which removes it from the cell array trenches (5). The auxiliary layer (24) allows the gate oxide (20) to be patterned without a complex mask process. An edge trench (7), with an electrode, on the potential of the field electrode structure (11) shields the cell array (3) from a drain potential.