Method to improve profile control and N/P loading in dual doped gate applications
US7186661B2 · kind B2 · utility
2Cited by
12References
3Claims
0Family size
Assignee
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Key dates
| Filing date | Jun 27, 2003 |
| Grant date | Mar 6, 2007 |
| Priority date | — |
| Expiry date | Jan 25, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for etching a polysilicon gate structure in a plasma etch chamber is provided. The method initiates with defining a pattern protecting a polysilicon film to be etched. Then, a plasma is generated. Next, substantially all of the polysilicon film that is unprotected is etched. Then, a silicon containing gas is introduced and a remainder of the polysilicon film is etched while introducing a silicon containing gas. An etch chamber configured to introduce a silicon containing gas during an etch process is also provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.