High performance tunneling-biased MOSFET and a process for its manufacture
US7187000B2 · kind B2 · utility
5Cited by
8References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 16, 2005 |
| Grant date | Mar 6, 2007 |
| Priority date | — |
| Expiry date | Mar 16, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
Abstract
A semiconductor structure and a method for its manufacture are provided. In one example, the structure includes a well region doped with a first type dopant (e.g., a P-type or N-type dopant). A gate pedestal formed over the well region has two ends, one of which at least partially overlies the well region and is doped with the first type dopant. A dielectric layer is positioned between the gate pedestal and the well region. Source and drain regions formed on opposite sides of the gate pedestal within the well region are doped with a second type dopant opposite in type to the first type dopant.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.