Semiconductor device including dual damascene interconnections
US7187085B2 · kind B2 · utility
13Cited by
12References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 26, 2004 |
| Grant date | Mar 6, 2007 |
| Priority date | — |
| Expiry date | Jan 4, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method (and structure) of forming an interconnect on a semiconductor substrate, includes forming a relatively narrow first structure in a dielectric formed on a semiconductor substrate, forming a relatively wider second structure in the dielectric formed on the semiconductor substrate, forming a liner in the first and second structures such that the first structure is substantially filled and the second structure is substantially unfilled, and forming a metallization over the liner to completely fill the second structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.