Circuit and method for testing a circuit having memory array and addressing and control unit
US7188291B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 12, 2004 |
| Grant date | Mar 6, 2007 |
| Priority date | — |
| Expiry date | Mar 30, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/48
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit configuration for testing a circuit using a test device for providing a test mode, where test procedures are performed sequentially. The test procedures involve comparing actual data that are output by the circuit under test with prescribed nominal data in the test device. A combinational logic device for logically combining the sequentially output test results is provided such that result data indicate fault free operation of the circuit under test only if the actual data which are output match the prescribed nominal data in all of the sequentially performed test procedures. The result data is output via an addressing and control unit in the circuit under test.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.