Method of manufacturing a semiconductor device having a multi-layered wiring structure
US7189637B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Dec 11, 2003 |
| Grant date | Mar 13, 2007 |
| Priority date | — |
| Expiry date | Feb 12, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/14
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An insulating portion of the respective wiring layers for a semiconductor device is constituted of insulating films. The one insulating film is made of a material whose conductivity is higher than that of the other insulating film that is made of an ordinary silicon oxide film and is provided in contact with the wiring. An electric charge accumulated in the wiring generated in the course of manufacture of the semiconductor device is discharged through the one insulating film at a stage where a charge accumulation in the wiring is low. This permits the heat release value generated through the discharge can be suppressed to a low level, and the short-circuiting failure between adjacent wirings can be suppressed or prevented.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.