One transistor flash memory cell

US7190022B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Danny Pak-Chum Shum · Poughkeepsie, US
• Georg Tempel · Zorneding, DE
• Ronald Kakoschke · Birkenfeld, DE

Key dates

• Filing date: Mar 16, 2005
• Grant date: Mar 13, 2007
• Expiry date: Mar 16, 2025

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B69/00

Abstract

An integrated circuit has a high voltage area, a logic area and a memory array for forming a system on a chip that includes linear, logic and memory devices. The memory array has floating gate transistors disposed in a triple well structure with a raised drain bit line 13 substantially vertically aligned with a buried source bit line 14. The memory array separates the columns with deep trenches 46 that may also be formed into charge pump capacitors.