Low stress flip-chip package for low-K silicon technology
US7190082B2 · kind B2 · utility
4Cited by
3References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 24, 2003 |
| Grant date | Mar 13, 2007 |
| Priority date | — |
| Expiry date | Dec 9, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/10253
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An underfill includes a base material and a filler material added to the base material wherein the filler material constitutes a selected percentage by weight of the underfill to provide an optimum balance between interfacial die stress and solder bump strain for next generation, Cu, low-K silicon technology.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.