Method of and program product for performing gate-level diagnosis of failing vectors
US7191374B2 · kind B2 · utility
6Cited by
21References
35Claims
0Family size
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Key dates
| Filing date | May 12, 2003 |
| Grant date | Mar 13, 2007 |
| Priority date | — |
| Expiry date | Feb 4, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/3177
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method of fault diagnosis of integrated circuits having failing test vectors with observed fault effects using fault candidate fault-effects obtained by simulation of a set of test vectors, comprises determining a fault candidate diagnostic measure for each fault candidate, the fault candidate diagnostic measure having a fault candidate match metric, an observed fault effect mismatch metric and a fault candidate excitation metric, ranking fault candidates in decreasing diagnostic measure order; and identifying fault candidate(s) having the highest diagnostic measure as the most likely cause of observed fault effects.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.