Method and apparatus for processing a circuit description for logic simulation
US7191412B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 28, 2005 |
| Grant date | Mar 13, 2007 |
| Priority date | — |
| Expiry date | Sep 28, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/33
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Method and apparatus for processing a circuit description including a hierarchy of components for logic simulation is described. Each component is described using one of a first hardware description language (HDL) and a second HDL. A root component and each component in the hierarchy below the root component described using an HDL identical to that of the root component is elaborated up to a cross-language boundary. The root component is described using one of the first HDL or the second HDL and each component at the cross-language boundary is described using the other of the first HDL or the second HDL. Each component at the cross-language boundary is stored in one of a first vector associated with the first HDL or a second vector associated with the second HDL based on language. A connection is established between each component at the cross-language boundary and a respective parent component.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.