In-situ plug fill
US7192531B1 · kind B1 · utility
5Cited by
7References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 24, 2003 |
| Grant date | Mar 20, 2007 |
| Priority date | — |
| Expiry date | Jan 17, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/31138
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming damascene features in a dielectric layer over a barrier layer over a substrate is provided. A plurality of vias are etched in the dielectric layer to the barrier layer with a plasma etching process in the plasma processing chamber. A patterned photoresist layer is formed with a trench pattern. Within a single plasma process chamber a combination via plug deposition to form plugs in the vias over the barrier layer and trench etch is provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.