Forming dual metal complementary metal oxide semiconductor integrated circuits
US7192856B2 · kind B2 · utility
11Cited by
1References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 18, 2005 |
| Grant date | Mar 20, 2007 |
| Priority date | — |
| Expiry date | Apr 14, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Complementary metal oxide semiconductor metal gate transistors may be formed by depositing a metal layer in trenches formerly inhabited by patterned gate structures. The patterned gate structures may have been formed of polysilicon in one embodiment. The trenches may be filled with metal by surface activating using a catalytic metal, followed by electroless deposition of a seed layer followed by superconformal filling bottom up.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.