Transistor with independent gate structures
US7192876B2 · kind B2 · utility
15Cited by
51References
39Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 22, 2003 |
| Grant date | Mar 20, 2007 |
| Priority date | — |
| Expiry date | Dec 16, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0245
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of making a transistor with independent gate structures. The gate structures are each adjacent to sidewalls of a semiconductor structure. The method includes depositing at least one conformal layer that includes a layer of gate material over a semiconductor structure that includes the channel region. A planar layer is formed over the wafer. The planar layer has a top surface below the top surface of the rat least one conformal layer at a location over the substrate. The at least one conformal layers are etched to remove the gate material over the semiconductor structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.