ESD protection structure and method utilizing substrate triggering for a high-voltage tolerant pad
US7193274B2 · kind B2 · utility
3Cited by
1References
8Claims
0Family size
Assignee
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Key dates
| Filing date | May 27, 2004 |
| Grant date | Mar 20, 2007 |
| Priority date | — |
| Expiry date | May 6, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/811
Abstract
In an ESD protection structure and method utilizing substrate triggering for a high-voltage tolerant pad on a substrate, an ESD protection device has a source connected to the pad and a gate and a drain both connected to a ground, and a substrate-triggering control circuit is used to keep the substrate at a low voltage during a normal operation, and pumping the substrate to a high voltage during an ESD event for the ESD protection device to be triggered much easier. The substrate-triggering control circuit is implemented with an active device, thereby reducing the chip size for the circuit and the loading effect on the pad.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.