Memory system and method to reduce reflection and signal degradation
US7194572B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 8, 2003 |
| Grant date | Mar 20, 2007 |
| Priority date | — |
| Expiry date | Jul 7, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C5/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of the invention provide a memory command and address (CA) bus architecture that can accommodate higher CA data output frequencies with reduced signal degradation. For one embodiment of the invention the CA is divided on the motherboard and a CA signal component routed to each of two dual in-line memory modules (DIMMs) of a two-DIMM/channel memory bus design. The CA signal component on each DIMM is then routed sequentially through each dynamic random access memory (DRAM) chip on the respective DIMM. In one embodiment, after routing through each DRAM, the CA signal is terminated on the DIMM. In an alternative embodiment, the CA signal is terminated on the die at the last DRAM of each respective DIMM.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.