Event based test method for debugging timing related failures in integrated circuits
US7194668B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 11, 2003 |
| Grant date | Mar 20, 2007 |
| Priority date | — |
| Expiry date | Oct 22, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31937
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A test method for debugging failures of an IC device with use of an event based semiconductor test system is capable of distinguishing a timing related failure from other failures. The test method includes the steps of: applying a test signal to a DUT and evaluating a response output of the DUT, detecting a failure in the response output, identifying a reference clock signal related to the failure, identifying a portion of the reference clock signal that is directly related to the failure, and incrementally changing a timing of events for the identified portion of the reference clock signal to detect change in the response output from the DUT.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.