Design layout preparing method
US7194704B2 · kind B2 · utility
33Cited by
2References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 16, 2004 |
| Grant date | Mar 20, 2007 |
| Priority date | — |
| Expiry date | Mar 29, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/0271
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
There is disclosed a method of producing a design layout by optimizing at least one of design rule, process proximity correction parameter and process parameter, including calculating a processed pattern shape based on a design layout and a process parameter, extracting a dangerous spot having an evaluation value with respect to the processed pattern shape, which does not satisfy a predetermined tolerance, generating a repair guideline of the design layout based on a pattern included in the dangerous spot, and repairing that portion of the design layout which corresponds to the dangerous spot based on the repair guideline.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.