Method and fabricating semiconductor device
US7196004B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 23, 2004 |
| Grant date | Mar 27, 2007 |
| Priority date | — |
| Expiry date | Nov 11, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76897
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating a semiconductor device is capable of preventing a hard mask layer of a conductive structure from being damaged during a self-aligned contact etching process. The method includes the steps of: forming a plurality of conductive structures including a conductive layer and a hard mask layer on a substrate; sequentially forming a first nitride layer, an oxide layer, a second nitride layer, and an etch stop layer on the plurality of conductive structures; forming an inter-layer insulation layer on the etch stop layer; and performing a self-aligned contact (SAC) etching process selectively etching the inter-layer insulation layer, the etch stop layer, the second nitride layer and the oxide layer until the SAC etching process is stopped at the first nitride layer to thereby form a contact hole exposing the first nitride layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.