Plasma damage protection circuit for a semiconductor device
US7196369B2 · kind B2 · utility
4Cited by
34References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 15, 2002 |
| Grant date | Mar 27, 2007 |
| Priority date | — |
| Expiry date | Nov 15, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/30
Abstract
A protection device and a method for manufacturing integrated circuit devices protect against plasma charge damage, and related charge damage during manufacture. The protection device comprises a dynamic threshold, NMOS/PMOS pair having their respective gate terminals coupled to the semiconductor bulk in which the channel regions are formed. With proper metal connection, the structure protects against plasma charge damage on the integrated circuit device during manufacture, and can also be operated to protect against abnormal voltages during operation of the circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.