Flash memory device
US7196372B1 · kind B1 · utility
35Cited by
5References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 8, 2003 |
| Grant date | Mar 27, 2007 |
| Priority date | — |
| Expiry date | Jul 8, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/62
Abstract
A non-volatile memory device includes a substrate, an insulating layer, a fin, an oxide layer, spacers and one or more control gates. The insulating layer is formed on the substrate and the fin is formed on the insulating layer. The oxide layer is formed on the fin and acts as a tunnel oxide for the memory device. The spacers are formed adjacent the side surfaces of the fin and the control gates are formed adjacent the spacers. The spacers act as floating gate electrodes for the non-volatile memory device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.