Single ended current-sensed bus with novel static power free receiver circuit
US7196548B2 · kind B2 · utility
3Cited by
7References
27Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 25, 2004 |
| Grant date | Mar 27, 2007 |
| Priority date | — |
| Expiry date | Dec 10, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/356191
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A single ended current sensed bus with novel static power free receiver circuit is described herein. In one embodiment, a receiver circuit example includes a latch circuit to latch values for a first output and a second output during an evaluation phase in response to an input, a pre-charge circuit coupled to the latch circuit to pre-charge the latch circuit during a pre-charge phase, and a static power dissipation blocking (SPDB) circuit coupled to the pre-charge circuit and the latch circuit to substantially block static power from being dissipated during the pre-charge phase. Other methods and apparatuses are also described.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.