Integrated clock supply chip for a memory module, memory module comprising the integrated clock supply chip, and method for operating the memory module under test conditions

US7196554B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Nazif Taskin · Birkenfeld, DE
• Manfred Proll · Dorfen, DE
• Manfred Dobler · Hersbruck, DE
• Gerald Resch · Calgary, CA

Key dates

• Filing date: Jul 7, 2004
• Grant date: Mar 27, 2007
• Expiry date: Sep 24, 2024

Classification

• Technology area (CPC G): Physics
• CPC primary: G11C11/401
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

An integrated chip has a clock signal input (1.1) for application of a first clock signal (clk1) and a clock signal output (1.2–1.5). Moreover, it has a phase locked loop (2), which, on the input side, is connected to the clock signal input (1.1) and serves far generating a second clock signal (clk2). Furthermore, the chip has a multiplexer (MUX), via which the first clock signal (clk1) or the second clock signal (clk2) can optionally be switched to the clock signal output (1.2–1.5), and a unit for frequency monitoring (3), which, on the input side, is connected to the clock signal input (1.1) and is designed and can be operated in such a way that, in the event of a limiting frequency (fmin) being undershot, the multiplexer (MUX) is caused to switch the first clock signal (clk1) to the clock signal output (1.2–1.5).