Memory array with current limiting device for preventing particle induced latch-up
US7196925B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 26, 2004 |
| Grant date | Mar 27, 2007 |
| Priority date | — |
| Expiry date | Apr 3, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/413
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device can include a group of memory cells, which can be arranged in a column (100) that receives power by way of a first cell supply nodes (106-0 to 106-m). A current limiter (110) can be situated between first cell supply nodes (106-0 to 106-m) and a power supply (VH), and limit a current (llimit) to less than a latch-up holding current (lhold_lu) for the group of memory cells (100). In a particle event, such as an α-particle strike, a current limiter (110) can prevent a latch-up holding current (lhold_lu) from developing, thus preventing latch-up from occurring. Current limiter (110) can include p-channel transistors and/or resistors, and thus consume a relatively small area of the memory device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.