Charge-sharing technique during flash memory programming
US7196938B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 20, 2005 |
| Grant date | Mar 27, 2007 |
| Priority date | — |
| Expiry date | Sep 20, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A non-volatile memory cell array, such as a Flash NOR array, is programmed by applying voltages to bit lines that connect to memory cells in the memory cell array. A first bit line corresponding to a first memory cell in the memory array may be turned on to perform a first programming operation for the first memory cell and second bit line corresponding to a second memory cell in the memory array may be turned on to perform a second programming operation that is configured to complete after the first programming operation. The turning on/off of the first and second bit lines may be overlapped to share charge between the first and second bit lines. This overlapping can reduce wasted power and decrease programming pulse overshoot problems.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.